WANG Zheng

Dr.-Ing. Zheng Wang earned the Bachelor degree in physics from Shanghai Jiao Tong University (SJTU), China and Master degree in Electronic Engineering from Technische Universit？t München (TUM), Germany. From 2008 till 2009, he worked in the mobile sector of Infineon Technologies AG in Munich (currently Intel Mobile Communications). In 2010 he joined as a research associate in the Institute for Communication Technologies and Embedded Systems (ICE) of RWTH-Aachen University, Germany, where he obtained the PhD (Dr.-Ing.) in the year 2015. From 2015 till 2016, he worked in the Bio-inspired Reconfigurable Analog INtegrated (BRAIN) Systems Lab, Nanyang Technological University, Singapore in the field of neuromorphic ASIC and hardware security. In 2017 he joined the Center for Automotive Electronics, Shenzhen Institutes of Advanced Technology as an Assistant Professor.

The research interests of Dr.-Ing. Wang include the design of digital processor and system, low-power and error-resilient architecture, hardware platform of neuromorphic computing. During PhD, he has published 20+ papers in well-known international conferences (e.g. DAC, DATE, GLSVLSI, ISCAS, ISQED). The reliability-aware high-level synthesis tool flow developed by him was demonstrated in DAC13 and DAC14. He has participated several international research projects funded by European Union, German Research Foundation, and Singaporean and Chinese grant agencies. He has successfully taped-out one mixed-signal Extreme Learning Machine (ELM) processor with 65nm CMOS technology, which achieves the peak performance of 1.36TOPS/W.

1. Modeling of neural network and its hardware acceleration

2. Low power and reliability-driven design of architecture and multiprocessor system

3. Design automation for digital IC

Representative Publications

(1)   Wang, Zheng(#)(*), Chattopadhyay, Anupam: High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, ISBN: 978-981-10-1073-6, Springer, 2017.

(2)   Wang, Zheng(#),  Chen, Yi,  Aakash, Patil, Jayabalan, Jayasanker, Zhang, Xueyong, Chang, Chip Hong and Basu, Arindam(*): Current Mirror Array: A novel circuit topology for combining Physical Unclonable Function and Machine Learning, IEEE Transactions on Circuits and Systems I: Regular Papers (under review)

(3)   Wang, Zheng(#)(*), Chen,Yi, Patil, Aakash, Chang, Chip Hong and Basu, Arindam: Current Mirror Array: a Novel Lightweight Strong PUF Topology with Enhanced Reliability, International Symposium on Circuits & Systems (ISCAS), Baltimore, 2017.5.28-2017.5.31

(4)   Wang, Zheng(#)(*)，Karakonstantis, Georgios，Chattopadhyay, Anupam，A low overhead error confinement method based on application statistical characteristics，Design Automation and Test in Europe (DATE)，Dresden，2016.3.1 4-2016.3.18

(5)   Wang, Zheng(#)(*)，Littarru, Alessandro，Ugwu, Emmanuel Ikechukwu，Kanwal, Shazia，Chattopadhyay, Anupam，Reliable many-core system-on-chip design using K-Node fault tolerant graphs，IEEE Computer Society Annual Symposium on VLSI (ISVLSI)，United States，2016.7.11-2016.7.13

(6)   Wang, Zheng(#)(*)，Yang, Liu，Chattopadhyay, Anupam，Architectural reliability estimation using design diversity，International Symposium on Quality Electronic Design (ISQED)，Santa Clara，2015.3.2-2015.3.4

(7)   Wang, Zheng(#)(*)，Xie, Hui，Chafekar, Saumitra，Chattopadhyay, Anupam， Architectural error prediction using probabilistic error masking matrices，Asia n Symposium on Quality Electronic Design (ASQED)，Kuala Lumpur，2015.8.4-2015.8 .5

(8)   Wang, Zheng(#)(*)，Chen, Chao，Sharma, Piyush，Chattopadhyay, Anupam，System-level reliability exploration framework for heterogeneous MPSoC，Great Lakes Symposium on VLSI (GLSVLSI)，Houston，2014.5.21-2014.5.23

(9)   Wang, Zheng(#)(*)，Paul, Goutam，Chattopadhyay, Anupam，Processor design with asymmetric reliability，IEEE Computer Society Annual Symposium on VLSI (ISVLSI)，Tampa，2014.7.9-2014.7.11

(10)   Wang, Zheng(#)(*)，Li, Renlin，Chattopadhyay, Anupam，Opportunistic redundancy for improving reliability of embedded processors，International Design & Test Symposium (IDT)，Marrakech，2013.12.16-2013.12.18

(11)   Wang, Zheng(#)(*)，Singh, Kapil，Chen, Chao，Chattopadhyay, Anupam，Accu rate and efficient reliability estimation techniques during adl-driven embedded processor design，Design Automation and Test in Europe (DATE)，Grenoble，2013.3 .18-2013.3.22

(12)   Wang, Zheng(#)(*)，Wang, Lai，Xie, Hui，Chattopadhyay, Anupam，Power modeling and estimation during ADL-driven embedded processor design，Internatio nal Conference on Energy Aware Computing Systems & Applications (ICEAC)，Istanbul，2013.12.16-2013.12.18

(13)   Wang, Zheng(#)(*)，Chen, Chao，Chattopadhyay, Anupam，Fast reliability exploration for embedded processors via high-level fault injection，Internation al Symposium on Quality Electronic Design (ISQED)，Santa Clara，2013.3.4-2013.3 .6

(14)   Wang, Zheng(#)(*)，Wang, Xiao，Chattopadhyay, Anupam，Rakosi, Zoltan E. ，ASIC synthesis using Architecture Description Language， International Symposium on VLSI Design, Automation & Test (VLSI-DAT)，Hsinchu，2012.4.23-2012 .4.25

(15)   Constantin, Jeremy(#)(*)，Wang, Zheng，Karakonstantis, Georgios，Chattopadhyay, Anupam，Burg, Andreas，Statistical fault injection for impact-evaluation of timing errors on application performance，Design Automation Conference (DAC)，Austin，2016.6.5-2016.6.9

(16)   Bian, Song(#)(*)，Shintani, Michihiro，Wang, Zheng，Hiromoto, Masayuki，Chattopadhyay, Anupam，Sato, Takashi，Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control，Asian Test Symposium (ATS)，Hiroshima，2016.11.21-2016.11.24

(17)   Marcu, Marius(#)(*)，Boncalo, Oana，Ghenea, Madalin，Amaricai, Alexandru，Weinstock, Jan，Leupers, Rainer，Wang, Zheng，Georgakoudis, Giorgis，Nikolopoulos, Dimitrios S.，Cernazanu-Glavan, Cosmin，Bara, Lucian，Ionascu, Marian，Low-cost hardware infrastructure for runtime thread level energy accounting，International Conference on Architecture of Computing Systems (ARCS)，Nuremberg，2016.4.4-2016.4.7

(18)   Cernazanu-Glavan, Cosmin(#)(*)，Marcu, Marius，Amaricai, Alexandru，Fedeac, Stefan，Ghenea, Madalin，Wang, Zheng，Chattopadhyay, Anupam，Weinstock, Jan，Leupers, Rainer，Direct FPGA-based power profiling for a RISC processor，Instrumentation and Measurement Technology Conference (I2MTC) ，Pisa，2015.5.11-2015.5.14

(19)   Rakosi, Zoltan Endre(#)(*)，Wang, Zheng，Chattopadhyay, Anupam，Adaptive energy-efficient architecture for WCDMA channel estimation，International Conference on Reconfigurable Computing and FPGAs (ReConFig)，Cancun，2011.11.30-2011.12.2

(20)   Rákossy, Zoltán Endre(#)，Wang, Zheng，Chattopadhyay, Anupam(*)，High-level design space and flexibility exploration for adaptive, energy-efficient WCDMA channel estimation architectures，International Journal of Reconfigurable Computing，2012.01.01, 2012

zheng.wang@siat.ac.cn

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